The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
One challenge to semiconductor fabrication is alignment. Semiconductor fabrication involves forming several patterned layers on top of each other. Each of these layers must be precisely aligned, or else the final device may not function correctly.
Alignment techniques often involve the use of alignment marks. For example, various layers to be patterned on a substrate may include alignment marks that are used to align with other formed layers. Matching alignment marks are formed within patterns of the subsequently formed layers. These matching alignment marks are placed within the patterns of the subsequent layers such that when aligned with the corresponding alignment marks of the underlying layers, both layers are aligned. But, such alignment techniques are not perfect because the subsequent patterns may be prone to stretching and twisting. Thus, it is desirable to have alignment techniques that provide improved alignment.